1. Field of the Invention
The present invention relates to a semiconductor memory device with a hierarchical arrangement of data lines.
2. Description of the Background Art
In recent years, with the advancement of high density integration of semiconductor memory devices, the number of memory bits integrated on a chip increases. In a semiconductor memory device such as a dynamic RAM, a larger number of memory cells, bit lines and word lines have been arranged in the memory cell array, thus increasing the area of the memory cell array region. As a result, the length of a data line transmitting information of a bit line externally from the memory cell array increases, which increases a floating capacitance for the data line, and reading and writing operations are delayed.
In order to solve this problem, dynamic RAMs having hierarchically arranged data lines have been suggested.
FIG. 29 is a diagram showing the configuration of a memory cell array in a dynamic RAM having a conventional hierarchical arrangement of data lines. In FIG. 29, MCA is the memory cell array, RB1 to RBn row blocks provided corresponding to RD1 to RDn and receiving a row select signal through a word line WL, CD1 and CD2 column decoders selectively outputting a column select signal in response to a column address signal, CB1 and CB2 column blocks provided corresponding to CD1 and CD2, respectively and receiving a column select signal through a column select line CSL, SD1 to SDn sense amplifier block decoders provided corresponding to RD1 to RDn, respectively for outputting a block select signal when a corresponding row decoder is activated and outputs a row select signal to a row block, and SB1 to SBn are sense amplifier blocks provided corresponding to SD1 to SDn, respectively and receiving a block select signal through block select signal lines BS, /BS ("/" is for a complementary signal line). Note that only one of block select signal lines BS, /BS is shown for the purpose of simplification.
Row blocks RB1 to RBn have a plurality of word lines WL disposed in the direction of rows, and each word line WL is connected to a plurality of memory cells MC arranged in the direction of rows. The plurality of memory cells MC are each connected with one of bit lines BL, /BL, and each pair of bit lines BL, /BL is disposed in the direction of columns for a corresponding sense amplifier. The bit line pair is disposed parallel to a column select line CSL.
Sense amplifier blocks SB1 to SBn are provided with sense amplifier portions arranged corresponding to column select line CSL in the direction of rows, each sense amplifier portion has a sense amplifier circuit SA connected to a bit line pair BL, /BL in a corresponding row block for amplifying a potential difference between bit lines BL and /BL upon receiving an activation signal (not shown) from a corresponding sense amplifier decoder SD, and a switch CG (hereinafter referred to as column gate) connected to a bit line pair BL, /BL for electrically connecting bit line pair BL, /BL connected sense amplifier circuit SA to a sub data line pair LDL, /LDL upon receiving a column select signal through a column select line CSL in a corresponding column decoder CD. Note that only one of sub data lines LDL, /LDL is shown for the purpose of simplification.
One column block CB includes sub data line pairs LDL, LDL corresponding in number to sense amplifier blocks SB, and switches DG (hereinafter referred to as data line gate) corresponding in number to sense amplifier blocks SB connecting sub data line pairs LDL, /LDL to main data line pairs GDL, /GDL, respectively upon receiving a block select signal through block select signal lines BS, /BS from sense amplifier decoder SD. Note that only one of such main data line pairs GDL, /GDL is shown for the purpose of simplification.
One column block CB has a plurality of main data line pairs GDL, /GDL, the number of which is determined by the number of row decoders RD which can be activated at a time. More specifically, in the configuration shown in FIG. 29, two pairs of main data lines are provided in one column block CB, and therefore the number of row decoders RD which can be activated at a time is at most 2. However a combination of sense amplifier blocks SD1 and SDn-1 or SD2 and SDn having data line gates connected to the same main data line pair causes data collision, and therefore their row decoders RD cannot be activated at a time.
Main data line pairs GDL, /GDL are all connected to respective circuit blocks (not shown) corresponding to respective main data line pairs in a data line input/output circuit PW including a preamplifier and a writing circuit.
FIG. 30 is a diagram showing in detail column gate CG and memory cell MC. As illustrated in FIG. 30, column gate CG is formed of transfer gates which electrically connects bit line BL and sub data line LDL, and electrically connects bit line /BL and sub data line /LDL in response to a high logic signal transmitted to column select line CSL. Memory cell MC is formed of an nMOS transistor having a gate electrode connected to word line WL and a capacitor.
FIG. 31 shows data line gate DG in detail. As illustrated in FIG. 31, data line gate DG is formed of nMOS transistors Q101, Q102, and pMOS transistors Q103, Q104 which electrically connect sub data line LDL and main data line GDL, and sub data line /LDL and main data line /GDL.
The operation of the configuration shown in FIGS. 29 to 31 will be described by way of illustrating a case in which the content of memory cell MC as shown in FIG. 30 is read out. Assume, for example, that row decoder RD1 is activated, word line WL11 is selected, and the column select line CSL11 of column decoder CD1 and the column select line SCL21 of column decoder CD2 are selected. Row decoder RD1 is activated, then row decoder RD1 outputs a high logic signal as a row select signal through word line WL11 in row block RB1. This activates memory cell MC connected to word line WL11, and the capacitor and bit line BL are turned on. Meanwhile, sense amplifier decoder SD1 corresponding to row decoder RD1 is activated in association with row decoder RD1, and sense amplifier circuit SA in the sense amplifier portion is activated through a signal line (not shown) in corresponding sense amplifier block SB1. Then, activated sense amplifier circuit SA amplifies a potential difference between bit lines BL and /BL connected thereto.
Then, high logic signals as column select signals are applied from column decoders CD1 and CD2 through column select signal lines CSL11 and CSL21, respectively. Thus, column gates CG111 and CG121 in the sense amplifier portions, respectively connected to column select signal lines CSL11 and CSL21 are turned on. The bit line pair and the sub bit line pair are electrically connected as a result. As the time, sub data lines LDL11, /LDL11 are connected to the amplified bit lines BL111 and /BL111, and sub data lines LDL12, /LDL12 are connected to the amplified bit lines BL121 and /LBL121. (Hereinafter a data line pair will be denoted only with LDL with /LDL being omitted. This applies to bit line pair BL, and main data line pair GDL). Meanwhile, no amplified signal will appear on other sub data line pairs whose sense amplifier circuits are not activated.
When a single data line gate DG11 provided for sense amplifier block SB1 and column block CB1, and a single data line gate DG21 provided for sense amplifier block SB1 and column block CB2 are provided with a high logic signal on block select signal line BS or a low logic signal on /BS through block select signal lines BS1, /BS1 from the common sense amplifier decoder SD1, sub data line pair LDL11 and main data line pair GDL11 are electrically connected as a result, and sub data line pair LDL12 and main data line GDL21 are electrically connected as well.
Thus, the data of memory cells connected to word line WL11 and to one bit line of bit line pair BL111 and one bit line of pair BL121 are output to an output circuit block (not shown) corresponding to main data line pair GDL11 in data line input/output circuit PW through sub data line pair LDL11, and main data line pair GDL11, respectively, and to an output circuit block (not shown) corresponding to main data line pair GDL21 in data line input/output circuit PW through sub data line pair LDL12 and main data line pair GDL21, respectively.
As described above, since in a conventional semiconductor memory device, in data reading, charges accumulated in one sub data line is discharged for one sense amplifier portion connected to one sub data line pair, and another sub data line paired therewith is charged from the sense amplifier portion, as the wiring length of the sub data pair increases, the floating capacitance of the wiring increases as well, and time required for charge/discharge increases, thus impeding high speed data transmission. In addition, power consumed for such charge/discharge increases as well. The same applies to any selected main data line, and thus power consumed by the entire semiconductor memory device increases. For expected increase in the storage capacity of semiconductor memory devices in the future, optimization of wiring arrangement for sub data lines or main data lines is a significant object.
More specifically, conventionally for the length of sub data lines in one sense amplifier corresponding to one column block (when 256 sense amplifier portions correspond to one column block), a length for connecting at least 256 sense amplifier portions is necessary. With increase in storage capacity, however, even advanced fine working techniques cannot prevent increase in the wiring length of sub data lines in a conventional arrangement in which sense amplifier portions are simply doubled, and column gates CD doubles, which increases floating capacitance or the like present in the sources/drains of transistors constituting the column gates. This impedes high speed data transmission and power consumption for charge/discharge of sub data lines inevitably increases.
With advancement of fine working techniques, memory cells may shrink in size in the future, but it would be difficult to improve the integration density of sense amplifier portions as much as memory cells shrink, for the complexity of the circuit configuration. A sense amplifier portion has an elongate shape in the direction of columns, and therefore increasing the numbers of row blocks and sense amplifier blocks corresponding to the row blocks increases the length in the direction of columns, which increases the wiring length of main data lines, and floating capacitance for the wiring increases as well, thus impeding high speed data transmission with power consumed for charge/discharge of main data lines increasing.